Reference:

Mark D. Aagaard, Robert B. Jones, and Carl-Johan H. Seger. Formal verification using parametric representations of Boolean constraints. In Design Automation Conference (DAC), pages 402-407. ACM Press, June 1999.

Abstract:

We describe the use of parametric representations of Boolean predicates to encode data-space constraints and significantly extend the capacity of formal verification. The constraints are used to decompose verifications by sets of case splits and to restrict verifications by validity conditions. Our technique is applicable to any symbolic simulator. We illustrate our technique on state-of-the-art Intel designs, without removing latches or modifying the circuits in any way.

Download (please read copyright notice):

PostScript (gzipped)
PDF (auto-translated from PS, may have problems)

BibTeX entry:

@InProceedings{AagaardJonesSeger99DAC,
  author    = {Mark D. Aagaard and 
               Robert B. Jones and 
               Carl-Johan H. Seger},
  title     = {Formal Verification Using Parametric Representations of
               {B}oolean Constraints},
  pages     = {402--407},
  month     = {June},
  year      = 1999,
  booktitle = {Design Automation Conference (DAC)},
  publisher = {ACM Press},
}